# Release qualification for DC-E02

Status: **BLOCKED**, physical samples recorded: **0**. No procedure below has been completed by this digital session. Supply measurements must be obtained with current-limited bench equipment before connecting a battery. Fabrication, charging and user operation are separate decisions.

| Gate | Required result and evidence | Current gap |
|---|---|---|
| Native electrical CAD | Save exact native KiCad ERC/DRC reports, investigate all errors, verify schematic/board agreement, and inspect actual plot/drill outputs. | Completed: native10.0.6 A04 ERC0/DRC0/unconnected0/parity0, plus five custom fault detections and actual plots/drills. Physical release gates below remain open. |
| Assembly and AVL | Confirm exact passive, socket, wire, switch and connector MPNs; check footprints against drawings; inspect polarity/keying, crimp tooling, wire restraint and reflow limitations. | Several carrier passive MPNs and keyed harness components remain unspecified. |
| Battery identity | Supplier/lot/chemistry/capacity/charge limits, received dimensions, actual connector polarity, protection circuit and cutoff behavior documented. Pouch is not compressed by the tray or wiring. | Only product/link evidence exists; there is no received pack. |
| Charge-temperature circuit | Release an actual hardware solution that prevents charging outside the selected cell's permitted range at tolerance. Include thermistor open/short, detached sensor and attachment lag. Verify current reaches the required disabled state at both boundaries. | BQ thermistor connection is present; complete 0–45 °C envelope compliance is not demonstrated. Do not enable battery charging on this basis alone. |
| Operating undervoltage | Define and implement a system shutdown and restart strategy before cell voltage violates the selected operating limit. Test startup, brownout, shutdown load and repeated reconnect behavior. | Pololu SHDN defaults enabled; protected PCM is not a qualified 3.0 V system UVLO. |
| Battery lead protection | Choose an inline positive-lead fuse and holder; coordinate with battery PCM, wire ampacity, connector current and fault energy. Verify normal peaks do not nuisance trip. | Carrier F1 is downstream of the charger's OUT terminal; it does not replace the pack-lead fuse. |
| Charger programming | Verify opened factory jumpers, isolated ISET path and actual 3.57 kΩ resistance. Measure charge current with battery simulator across source/cell voltage and temperature corners. Confirm EN1/EN2 and input current limit. | Calculated current is 221–276 mA at source/resistor corners; no measured current or reworked module exists. |
| Load sharing and timer | With a battery simulator, log USB input, system OUT and battery current through USB connect/disconnect, depleted/full battery and display/radio load transitions. Confirm charge termination and timer behavior during system use and sleep. | At the 1 W allowance the ideal 500 mA input leaves about 216 mA for charging. Neither full-rate charging nor full-charge completion is guaranteed. |
| Converter and compute | Measure 5 V and 3.3 V rails at module and load terminals during boot, display activity, radio bursts and input switching. Record transient minima/maxima, resets and current-limiter activity. | 1 W continuous and 2.25 W burst are engineering allowances, not measured demand or validated converter capacity. |
| Closed-case temperature | Instrument charger IC/PCB, converter, diode, fuse, compute regulator and pack surface at declared ambient limits and worst actual load. Record steady state and charging transitions. Keep heat spreaders electrically insulated and away from the pouch and antenna. | No thermal model, sensor traces, junction estimates or closed-case samples exist. The 8 mm gap is a packaging choice. |
| USB and service isolation | Validate dedicated 5 V source and cable, both plug orientations, inrush, unplug behavior and intended current authorization. Confirm the service procedure removes XIAO before its USB port is connected. | No PD or Type-C current advertisement interpretation is implemented; host-computer compatibility is not certified. |
| Display and firmware | Compile/flash the exact target, verify all GPIO assignments, SD_CS idle isolation, eye rendering, brightness and button behavior. Measure signal quality on the chosen harness. | Pin assignments and hardware connections exist; target build and device behavior remain untested. |
| Optional audio | Select speaker impedance/power, BTL wiring, sound level, supply limit and physical location. Verify neither BTL output is grounded; measure temperature and distortion at the released volume. | Amplifier and speaker are DNP in the base configuration. |
| Mechanical and RF | Verify actual component heights, connector mating/withdrawal paths, fastener/wire interference, battery retention and the full antenna reservation in the final native assembly. Test RF performance with the selected antenna and enclosure. | Prime integrates the numeric geometry. Component fit is not a received-part measurement or RF test. |

Record each sample's date, operator, instrument, calibration reference, source CAD hashes, parts/firmware revisions, setup photograph, numeric trace file and verdict. Failed, missing or unrelated-source evidence leaves the relevant gate open. Fault injection for electrical safety should use a battery simulator and appropriate current limitation; do not use the pouch as a sacrificial short-circuit source.